Signal processing circuit

ABSTRACT

A signal processing circuit comprises a difference stage for receiving an input signal to be processed and a feedback signal taken from an output signal of the circuit. The difference stage generates a difference signal corresponding to the difference between the input and feedback signal. An integrator stage is coupled to the difference stage to receive the difference signal and output an integrated signal. A time continuous pulse width modulating stage is coupled to the integrator stage to receive the integrated signal and to modulate the signal with reference to a continuously varying carrier signal. A continuous time feedback path is coupled to the output of the modulating stage and an input or the difference stage. The integrator stage comprises at least two integrators to provide second or higher order integration.

The present invention relates to a signal processing circuit.Particularly, but not exclusively, the invention relates to an amplifiercircuit such as an audio power amplifier.

Audio power amplifier systems have traditionally used linear (class A orclass AB) amplifiers. Linear amplifiers are, however, inherentlyinefficient. Heat dissipation and power supply requirements of linearamplifiers can be particularly problematical in modern electronicconsumer products such as personal computers and multi-media systems.This has lead to the development of various alternative approaches toaudio amplification.

One such approach is the “switching”, or Class-D, amplifier.Essentially, Class-D amplifiers work by varying the duly cycle of apulse width modulated (PWM) signal. A Class-D amplifier essentiallycomprises a continuous time pulse width modulator coupled between audioinput and power output stages. The pulse width modulator comprises acomparator which receives the input audio signal and a reference carriersignal which continuously varies at the desired switching frequency(typically ten times the highest frequency of the desired audio output).

The reference signal can be any periodic signal but is usually acontinuous triangular wave (typically plus or minus 5 volts). The outputof the modulator is a rapidly switching square wave which is fed to theoutput stage. The output stage transistors (typically power mosfets in aH-bridge configuration) therefore operate the majority of the timeeither fully on or fully off (ideally never operating in mid-conduction)which reduces power dissipation and increases efficiency. The resultingoutput signal is a rapidly switching square wave with a duty cycleproportional to the amplitude of the input audio signal. This may thenbe supplied to a speaker, via an output filter circuit if appropriate.

Conventional class D amplifiers have very high efficiency but relativelypoor distortion and noise performance and thus relatively poor soundquality.

An alternative type of amplifier with improved performance is thedelta-sigma amplifier. A delta-sigma amplifier may have an output stageidentical to that of a conventional Class-D amplifier but differs inthat delta-sigma modulation is used rather than time continuous pulsewidth modulation. In particular, a feedback structure, conventional indelta-sigma modulators, is used to improve performance. Thus, a typicaldelta-sigma amplifier comprises a time quantised comparator with afeedback path from the comparator output to a subtractor at which theoutput is compared to the audio input. The output of the subtractor issupplied to an integrator stage the output of which is input into thecomparator. The integrator integrates the error voltage so that thesystem constantly minimises the error by adjusting the output datastream.

A simple first order delta-sigma modulator comprises a singleintegrator. It is however loom to improve the performance of adelta-sigma modulator by using more than one integrator but such higherorder modulators can become difficult to stabilise. In particular, thetap coefficients needed to stabilise an nth order delta-sigma modulatorreduce the effectiveness of the feedback so that little benefit isgained by employing great 4th order.

Although improving on the performance of conventional Class-Damplifiers, delta-sigma amplifiers nevertheless suffer from significantdistortion and noise, principally due to the time sampling of thequantiser.

A Class-D amplifier with a feedback loop similar to that of adelta-sigma amplifier has been proposed. Essentially this employs afirst order integration stage which outputs to a time continuous pulsewidth modulator.

It is an object of the present invention to provide a power amplifiercircuit with reduced distortion and noise compared with conventionalamplifier circuits. The invention is not, however, limited to poweramplifier circuits. It is thus a more general object of the presentinvention to provide a signal processing circuit with improved noise anddistortion performance. According to the present invention there isprovided a signal processing circuit comprising:

-   -   a difference stage for receiving an input signal to be processed        and a feedback signal taken from an output signal of the circuit        the difference stage generating a difference signal        corresponding to the difference between the input and feedback        signal;    -   an integrator stage coupled to said difference stage to receive        said difference signal and outputting an integrated signal;    -   a time continuous pulse width modulating stage coupled to the        the integrator stage to receive the integrated sigal and to        modulate said signal with reference to a continuously varying        career signal; and    -   a continuous time feedback path coupled to the output of the        modulating stage and an input of the difference stage;    -   wherein the integrator stage comprises at least two integrator        to provide second or higher order integration.

The provision of second or higher order feedback significantly improvesperformance by reducing noise and distortion to negligible levels as isdiscussed further below.

Preferred embodiments of the invention take advantage of the highfeedback levels by utilising a spread spectrum carrier sigal to reducethe effect of electromagnetic emissions.

This aspect of the invention combines the inherent linearity of acontinuous time PWM modulator, and the very high level of correctivefeedback offered by the integrator stage, to correct for any systemerrors including, but not limited to,—power supply unit noise andmodulation, carrier distortions including spread-spectrum randomisation,output stage errors, dead time errors & comparator propagation delaydispersion errors.

For instance, designers have traditionally been force to shy away fromimplementing switching amplifiers or switching power supply in consumerelectronic devices due to there undesirable side effect of generating RFand electrical noise. Not only does this make trying to incorporate anyform of switching unit into a low noise, or RF sensitive design such asRF tuners, very difficult; products incorporating “switching basedtechniques” have received bad press due to there electrical noise andemissions causing intermodulation by-products within the audio bandsresulting in an undesirable “sonic signature”.

In consumer electronics the typically RF bands of interest are the “AM”band around 250 KHz to 1500 KHz, and the “FM” band from 88 MHz to about110 MHz. For the AM band, which is at the lower-end of the RF spectrum,the propagation effect of the conducted emissions (H-Field) is veryeffective. It is nearly impossible to shield against conductedemissions, i.e. magnetic component field leakage, within the confines ofa small-integrated “consumer” priced product. The only real practicalconventional solution for the AM band reception is to use a switchingfrequency above the highest required reception frequency. However themodulation bandwidth of the modulator (say 200 KHz), will be centered+/_ around the carrier frequency. Thus for AM reception up to 1600 KHz,this dictates a switching frequency above 1.8 MHz. For optimalefficiency the switching frequency should however be no more therequired.

Although switching above 1.8 MHz results in satisfactory AM performance,the same cannot be said for the FM band since switching units operatewith “squared waves”, which in theory can contain an infinite spectrumof “HF” components. Due to the higher frequency of these components, thepropagation of “E-field component” is very effective. Although screeningand high order filtering techniques can go a long way to reducing“B-field” emission problems, they can never be 100% effective. Thesemeasures also add too product cost aid complexity.

As RF emissions are harmonically spaced, they introduce discretecarriers within the “FM band”. This causes a severe problem with modernday “Auto Seek” receivers, which scan the “FM” band for carriers ofsignificant signal strength. Using switching units within such receiversresults in the “Auto Seek” level detectors stopping at every RF harmonicof the switching unit's carrier, making them practically useless.

The solution to this problem provided by the present invention is to usea spread-spectrum carrier. As the carrier is not correlated to the inputsignal, there will be no discrete harmonics of the carrier at higherfrequencies, just a lower level noise. This background noise will reducethe signal/noise ratio of the receiver, but will enable the tuningcircuits to function correctly in the presence of the switching carrier.

Traditionally spread spectrum techniques have not been possible for highperformance low distortion and noise switching applications. In aswitching based power supply unit for instance, a spread spectrumcarrier results in LF noise on the output rails, due to the normally lowlevels of feedback available. Satisfactory filtering of this LF noiserequires large value de-coupling capacitors and magnetics, both of whichare detrimental to the size and cost of the end product. Likewise in aswitching amplifier, modulation of the carrier results in poordistortion and noise performance. These problems are overcome by thepresent invention.

Another benefit of using a spread spectrum carrier is the randomisationof any aliasing distortion products demodulated within the audio band.100% HF/RF filtering of the input is not practical both in sonic andcost terms. Aliasing distortion artefacts are becoming increasingproblematic with the increasing use off “RF noisy” digital based audioinput sources such as CD and DVD players. By randomising the carrier,the resultant aliasing intermodulation products no longer cause discretetones on the noise floor, but are effectively randomised, gentlyincreasing the noise floor—a much preferable situation from a sonicpoint of view.

A specific embodiment of the present invention will now be described, byway of example only, with reference to the accompanying drawings, inwhich:

FIG. 1 is a simplified block diagram of a modulator circuit embodyingthe present invention;

FIG. 2 is a schematic circuit diagram of one preferred embodiment of theintegrator stage of the circuit of FIG. 1; and

FIG. 3 is a schematic circuit diagram of one preferred embodiment of amodulator stage of the circuit of FIG. 1.

Referring to FIG. 1, the illustrated circuit is a simple single endedmodulator which essentially consists of a difference stage comprising asubtractor 201; a fourth order integrator stage comprising four cascadedintegrators 202, 204, 206, 208 and an adder 209; and a continuous timepulse with modulating stage comprising a comparator 211 and referencecarrier signal generator 210. The modulator circuit receives an inputanalogue signal from an input stage 1 and delivers a pulse withmodulated output signal to an output stage 2. A feedback path isprovided between the output stage 2 and the subtractor 201.

In operation, the output signal is subtracted from the input signal atthe subtractor 201 and the resultant error signal is fed to the firstintegrator 202 of the integrator stage. The four integrators 202, 204,206 and 208 are cascaded and coupled together via tap coefficients 203,205 and 207 which are attenuators with values set appropriately toensure stability. The outputs of the four integrators are summed atadder 209 and the summed signal is fed to one input of the comparator211. The second input of the comparator 211 receives a continuouslyvarying reference carrier signal from the signal generator 210. Thecomparator quantifies the input signal with respect to amplitude andoutputs a pulse width modulated square wave of infinite resolution witha duty cycle which varies in proportion to the varying amplitude of theoriginal input signal.

The input and output stages may be entirely conventions and designed tosuite the particular application to which the invention is put. Forinstance, in an audio power amplifier application the input and outputstages may be conventional Class-D stages, the output stage for examplecomprising a power MOSFET switching stage coupled to an LC outputfilter. In such an application the feedback signal is taken from theoutput of the switching transistors. Similarly, the modulator stage maybe entirely conventional as is, for instance, found in a typical Class-Damplifier. The carrier signal may be any suitable periodic signal suchas a continuous triangular wave as is commonly used as a referencesignal in conventional Class amplifiers.

A fundamental difference between the circuit in accordance with thepresent invention and conventional modulating circuitry as found, forinstance, in Class-D amplifiers, is the provision of a greater thanfirst order integrator stage providing high levels of feedback whichsubstantially reduces noise and distortion in the output signal. Thenoise reduction is significantly greater than at that could be expectedfrom a first order modulator as for instance disclosed in the Motorolaapplication note referred to above. Indeed, with the present inventionall in band Class-D distortion is reduced to negligible levels,including distortion in the output stage, the comparator, the powersupply and the reference signal.

The invention also improves upon the performance of conventionaldelta-signal modulators by eliminating the distortion and noiseassociated with the inherently limited resolution of the discrete timequanitiser of a delta-sigma modulator. With the present invention theinput signal is quantised with respect to amplitude only so that theoutput has infinite time resolution.

Although, as mentioned above, the modulator stage, and in particular thecarrier signal generator, may be entirely conventional, preferredembodiments of the present invention employ spread spectrum techniquesto reduce radiated electromagnetic interference which manifests as noisein the RF spectrum. Essentially the high levels of global feedbackprovided by the integrator stage enables the application of conventionalspread spectrum techniques to the carrier signal generator to vary(either randomly or periodically) the frequency of the carrier to spreadthe energy of the signal and reduce correlated RF noise. Such techniquesare well known in communications systems but have not previously beenapplied in continuous pulse width modulator cats. For instance inconventional Class-D amplifier circuits a spread spectrum carrier signalwould not be contemplated since it would simply introduce unacceptablenoise into the audio output signal. With the present invention howeverthat noise is eliminated by the feedback.

A variety of different techniques may be envisaged to spread thespectrum of the carrier signal. The particular circuit implementation isnot important provided the resulting carrier signal has a spreadspectrum which is not correlated to the input signal (whether forinstance a truly random or “weighted” noise source).

Specific circuit implementations of the present invention areillustrated in FIGS. 2 and 3 which exemplify the application of theinvention, including a non-signal correlated carrier, in an audio poweramplifier circuit.

FIG. 2 shows a schematic of the integrator stage which is indifferential format for use with conventional Class-D H Bridge outputstages. Resistors R1, R2, R3 and R20 comprise the feedback resistors forthe amplifier and determine the gain. U1 is a combined subtractor andintegrator. U7 provides an inverted output in order to maintain improvedcommon mode performance of the input section R4, R5 and R22, R23 are thefirst tap coefficients. U2 is the second order integrator set up as adifferential to single ended converting integrator. R7 and R8 providethe second tap coefficient, U3 the third integrator, R10 and R11 thethird tap coefficient with the final integrator provided by U4. Theoutputs of each integrator are summed by U5 with the final analogueoutput voltage WOP. All the integrators are continuous time; thus theoutput is completely covered by the continuous feedback.

FIG. 3 shows the schematic of the pulse width modulator. This takes theoutput from the integrator stage and generates two out of phase pulsewidth modulated signals for each side of the H Bridge output. The outputfrom the integrator stage WOP is fed to two comparators U11 a and U11 bvia resistors r33 and r20. The threshold voltage is effectivelymodulated by mid a triangular waveforms of opposite phase via resistorsR32 R25. This comparator is low cost, but gives excellent performance,with low propagation delay error. The digital outputs are generated byU12, for feeding to the H Bridge outputs.

The two 180 deg. out of phase triangular waves are generated from a 3.5MHz clock input from the Spread-Spectrum VCO. This is divided by two, byflip-flop U9 generating 1.75 MHz. This has complementary square waveoutputs, which are fed to u6 and u10. These convert the square wave intoa triangular wave

In the above embodiment of the invention the carrier spectrum is spreadby modulating the clock. One possible alternative would be to introducenoise into the audio path by, for instance, adding a shaped noise sourceto the output of the modulator.

It will be appreciated by the that many modifications ban be made to thedetailed circuitry described above. Appropriate circuit designs toimplement the present invention in a wide variety of applications willbe apparent to the skilled person. In particular it will be understoodthat the invention is not limited to audio amplifier systems but can beused in any application requiring switched sigal modulation such as, forinstance, in a switched power supply nut. Many other possibleapplications of the invention will be readily apparent to theappropriately skilled person.

1. A signal processing circuit comprising: a difference stage for receiving an input signal to be processed and a feedback signal taken from an output signal of the circuit, the difference stage generating a difference signal corresponding to the difference between the input and feedback signal; an integrator stage coupled to said difference stage to receive said difference signal and outputting an integrated signal; a time continuous pulse width modulating stage coupled to the integrator stage to receive the integrated signal and to modulate said signal with reference to a continuously varying spread spectrum carrier signal non-correlated to the input signal; and a continuous time feedback path coupled to the output of the modulating stage and an input of the difference stage; wherein the integrator stage comprises at least two integrators to provide second or higher order integration.
 2. A signal processing circuit according to claim 1, wherein the modulating stage comprises a comparator which receives said integrated and reference carrier signals, and a reference signal generator which supplies a non-signal correlated spread spectrum carrier signal to said comparator.
 3. A signal processing circuit according to claim 2, wherein said reference signal generator comprises a clock which is modulated to spread the spectrum of the signal.
 4. A signal processing circuit according to claim 1, wherein the spectrum of the carrier signal is spread by introducing noise into the signal path before feedback to the difference stage.
 5. A signal processing circuit according to claim 1, further comprising a power switching stage having an input and an output, the input being coupled to the output of the modulator stage and the feedback path being couple to the output of the switching stage.
 6. A signal processing circuit according to claim 1, wherein the integrator stage comprises two or more cascaded integrators and an adder which sums the outputs of the integrators.
 7. A signal processing circuit according to claim 6, wherein said integrators are coupled together via tap coefficients which stabilize the integrator stage.
 8. A signal processing circuit according to claim 1, wherein the difference stage and integrating stage are combined by provision of a combined subtractor/integrator.
 9. A signal processing circuit according to claim 2, further comprising a power switching stage having an input and an output, the input being coupled to the output of the modulator stage and the feedback path being couple to the output of the switching stage.
 10. A signal processing circuit according to claim 3, further comprising a power switching stage having an input and an output, the input being coupled to the output of the modulator stage and the feedback path being couple to the output of the switching stage.
 11. A signal processing circuit according to claim 4, further comprising a power switching stage having an input and an output, the input being coupled to the output of the modulator stage and the feedback path being couple to the output of the switching stage.
 12. A signal processing circuit according to claim 2, wherein the integrator stage comprises two or more cascaded integrators and an adder which sums the outputs of the integrators.
 13. A signal processing circuit according to claim 3, wherein the integrator stage comprises two or more cascaded integrators and an adder which sums the outputs of the integrators.
 14. A signal processing circuit according to claim 4, wherein the integrator stage comprises two or more cascaded integrators and an adder which sums the outputs of the integrators.
 15. A signal processing circuit according to claim 5, wherein the integrator stage comprises two or more cascaded integrators and an adder which sums the outputs of the integrators.
 16. A signal processing circuit according to cliam 2, wherein the difference stage and integrating stage are combined by provision of a combined subtractor/integrator.
 17. A signal processing circuit according to claim 3, wherein the difference stage and integrating stage are combined by provision of a combined subtractor/integrator.
 18. A signal processing circuit according to claim 4, wherein the difference stage and integrating stage are combined by provision of a combined subtractor/integrator.
 19. A signal processing circuit according to claim 5, wherein the difference stage and integrating stage are combined by provision of a combined subtractor/integrator.
 20. A signal processing circuit according to claim 6, wherein the difference stage and integrating stage are combined by provision of a combined subtractor/integrator. 